The present invention relates generally to digital computer systems, and more specifically to systems having microcode for execution of complex macroinstructions.
Many modern computer architectures use microcode to support execution of complex macroinstructions. When a macroinstruction, or machine instruction, is read by the central processor, a jump is made to the appropriate microcode subroutine. This subroutine contains the code necessary to implement the macroinstruction.
Such an arrangement has numerous advantages. Single complex ideas can be expressed as one machine instruction. Thus, the programmer is relieved from the burden of producing code for these complex ideas. In addition, care can be taken to ensure that the most efficient microcode is used, which will generally result in more efficient code than that produced by many different programmers. The microcode can even be changed between versions of the same system without affecting programs written at the macroinstruction level.
One drawback of microcode machines is that microcode must be used to support all instructions. There is some minimum amount of processor overhead every time a microcode subroutine is executed. This is especially true with pipelined architectures which must flush the pipeline every time a jump to a microcode subroutine is made. This overhead means that many simple instructions are executed very inefficiently.
It would be desirable for a single computer architecture to have the ability to execute complex instructions, but to also be extremely efficient for execution of simple instructions. An ideal goal would be a system that can execute simple macroinstructions at the maximum microinstruction execution rate of the central processor, one macroinstruction per processor cycle.
It is therefore an object of the present invention to provide a mixed instruction set architecture which supports both complex and simple instructions. Simple instructions are preferably executed at a rate of up to one macroinstruction per clock cycle, while complex machine instructions are also supported.
Thus, a computer system designed according to the present invention uses microcode to support execution of complex instructions. When a new machine instruction, (macroinstruction) is read, the instruction code is used to index a special look-up table. If the macroinstruction is a simple type which has a corresponding single microinstruction, the entry in the look-up table contains that corresponding microinstruction. The system directly executes the microinstruction found in the look-up table, and then reads the next macroinstruction. If a particular macroinstruction is complex, and requires a microcode subroutine to execute, the corresponding entry in the look-up table is a jump instruction having a target which is the appropriate microcode subroutine.
This system can be combined with a pipelined architecture for increased throughput. When a pipelined architecture is used, a macroinstruction queue can be used to buffer macroinstructions. When a macroinstruction causes a jump to a microcode routine, the next macroinstructions are not lost, even through they are flushed somewhere in the pipeline. Macroinstructions not yet executed are retained in the queue until control returns from the microcode routine, at which time they re-enter the pipeline.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereafter appear, and for purposes of illustration, but not of limitation, a preferred embodiment is shown in the accompanying drawings.